1. Field of the Invention
The invention relates to a driving circuit for a liquid crystal display.
2. Related Background Art
FIG. 5 is a circuit diagram of a conventional liquid crystal driving circuit.
From the top of the diagram, (a) shows a positive polarity operating circuit, (b) shows a negative polarity operating circuit, and (c) and (d) show time charts for the operations of those operating circuits in order.
Referring to the diagram, the conventional driving circuit for a liquid crystal display has a positive polarity feedback amplifier AMP(P) and a negative polarity feedback amplifier AMP(N). A positive polarity input gradation voltage DAC(P) is inputted to a (+) terminal of the positive polarity feedback amplifier AMP(P). A positive polarity output gradation voltage OUT(P) is supplied to a parasitic capacitor C1 such as a signal line via a control switch SW3.
Further, a negative polarity input gradation voltage DAC(N) is inputted to a (+) terminal of the negative polarity feedback amplifier AMP(N). A negative polarity output gradation voltage OUT(N) is supplied to a parasitic capacitor C2 such as a signal line via the control switch SW3. The positive polarity feedback amplifier AMP(P) and the negative polarity feedback amplifier AMP(N) are connected as a pair to the two signal lines. Ordinarily, in many cases, those two signal lines are connected to two liquid crystal dots adjacently arranged on a liquid crystal display apparatus. Further, the connection of the positive polarity feedback amplifier AMP(P) and the connection of the negative polarity feedback amplifier AMP(N) are alternately switched between the signal lines at a predetermined time interval. Such a switching operation is performed in order to prolong a life span of the liquid crystal display apparatus.
The positive polarity feedback amplifier AMP(P) and the negative polarity feedback amplifier AMP(N) are voltage followers for outputting a voltage which is equal to an input voltage irrespective of magnitude of loads (parasitic capacitors C1 and C2 of the signal lines here). The voltage which becomes equal to ½ of a power voltage VDD is defined to be an intermediate voltage VM here.
An input voltage which is increased/decreased in the direction of the power voltage VDD in the case where the intermediate voltage VM is set to a reference voltage is defined as a positive polarity input gradation voltage DAC(P). An input voltage which is increased/decreased in the direction of a ground voltage VSS in the case where the intermediate voltage VM is set to the reference voltage is defined as a negative polarity input gradation voltage DAC(N). Similarly, an output voltage which is increased/decreased in the direction of the power voltage VDD in the case where the intermediate voltage VM is set to the reference voltage is defined as a positive polarity output gradation voltage OUT(P). An output voltage which is increased/decreased in the direction of the ground voltage VSS in the case where the intermediate voltage VM is set to the reference voltage is defined as a negative polarity output gradation voltage OUT(N).
That is, the positive polarity gradation voltage is a gradation voltage which increases like VU1, VU2, and VU3 toward the power voltage VDD in the case where the intermediate voltage VM is set to the reference. The negative polarity gradation voltage is a gradation voltage which increases like VD1, VD2, and VD3 toward the ground voltage VSS in the case where the intermediate voltage VM is set to the reference.
Ordinarily, for example, in the case of using a nematic liquid crystal, intensity of an electric field which is applied to the liquid crystal at the intermediate voltage VM becomes equal to 0 by another construction (not shown), so that the liquid crystal enters a state where it is difficult to transmit the light. On the other hand, the larger the positive polarity output gradation voltage OUT(P) or the negative polarity output gradation voltage OUT(N) is, the larger the intensity of the electric field which is applied to the liquid crystal is and the liquid crystal enters a state where it is easy to transmit the light. Therefore, even if the switching operation of the connection of the positive polarity feedback amplifier AMP(P) and the connection of the negative polarity feedback amplifier AMP(N) is executed between the two signal lines every predetermined elapse of time as mentioned above, a reproduced image is not influenced.
For example, a case where the positive polarity input gradation voltage DAC(P) and the negative polarity input gradation voltage DAC(N) which are line-symmetrical with respect to the intermediate voltage VM as a center are inputted to the positive polarity feedback amplifier AMP(P) and the negative polarity feedback amplifier AMP(N), respectively, will be described. Usually, since luminance levels of the adjacent dots are equal in many cases, such a state often occurs. FIGS. 5(c) and 5(d) show changes in each voltage in such a state.
FIG. 5(c) shows the time chart in the case where, for example, the positive polarity input gradation voltage DAC(P) which increases from VU1 to VU3 at time P1, decreases from VU3 to VU2 at time P2, and increases from VU2 to VU3 at time P5 is inputted to the positive polarity feedback amplifier AMP(P), respectively, and the negative polarity input gradation voltage DAC(N) which increases from VD1 to VD3 at time P1, decreases from VD3 to VD2 at time P2, and increases from VD2 to VD3 at time P5 is inputted to the negative polarity feedback amplifier AMP(N), respectively.
At this time, in the positive polarity feedback amplifier AMP(P), when the positive polarity input gradation voltage DAC(P) increases from VU1 to VU3 at time P1, the positive polarity output gradation voltage OUT(P) promptly traces VU3. However, when the positive polarity input gradation voltage DAC(P) decreases from VU3 to VU2 at time P2, although the positive polarity output gradation voltage OUT(P) is supposed to decrease to VU2 at time P3, it cannot trace such a voltage but decreases to reach VU2 at time P4. In the negative polarity feedback amplifier AMP(N), when the negative polarity input gradation voltage DAC(N) increases from VD1 to VD3 at time P1, the negative polarity output gradation voltage OUT(N) promptly traces VD3. However, when the negative polarity input gradation voltage DAC(N) decreases from VD3 to VD2 at time P2, although the negative polarity input gradation voltage OUT(N) is supposed to decrease to VD2 at time P3, it cannot trace such a voltage but decreases to reach VD2 at time P4.
Such a phenomenon is common to the voltage followers which are used as a positive polarity feedback amplifier AMP(P) and a negative polarity feedback amplifier AMP(N) to which a capacitive load is connected. That is, in the positive polarity feedback amplifier AMP(P), although the operation to increase the positive polarity output gradation voltage OUT(P) is fast, the operation to decrease the positive polarity output gradation voltage OUT(P) is slow. Such a fact is generally known. Also in the negative polarity feedback amplifier AMP(N), although the operation to increase the negative polarity output gradation voltage OUT(N) is fast, the operation to decrease the negative polarity output gradation voltage OUT(N) is slow. Such a fact is also generally known. In such a state, an image cannot be accurately reproduced onto a display screen of the liquid crystal display apparatus.
Therefore, when the switching operation of the connection of the positive polarity feedback amplifier AMP(P) and the connection of the negative polarity feedback amplifier AMP(N) is executed between the two signal lines at a predetermined time interval as mentioned above, the control switch SW3 is short-circuited, charges charged in the parasitic capacitors C1 and C2 are once returned to the intermediate voltage VM, and thereafter, the operation is started. A peripheral construction of the control switch SW3 will be described in detail hereinlater in the description of a preferred embodiment.
Meanwhile, constructions to prevent the occurrence of such a problem have also been laid open (for example, refer to JP-A-11-95729 (Page 5, FIG. 1) and JP-A-2002-229525 (Summary)).
The method whereby the control switch SW3 is short-circuited each time the connection switching of the positive polarity feedback amplifier AMP(P) and the negative polarity feedback amplifier AMP(N) is executed at a predetermined time interval, the charges charged in the parasitic capacitors C1 and C2 are once returned to the intermediate voltage VM, and thereafter, the operation is started as mentioned above, has the following problems to be solved. That is, when the connection switching is executed at a predetermined time interval, the operation is performed effectively. However, if a switching period becomes long, for example, twice as long as the predetermined time interval, three times as long as the predetermined time interval, . . . , a case where a signal level decreases in the same period occurs. In such a case, since the connection switching is not executed even if the signal level decreases, an inconvenience as mentioned above occurs. Therefore, the effect is small. This is because the voltages of the parasitic capacitors C1 and C2 are not returned to the intermediate voltage VM unless the connection switching is executed.
Even if the connection switching is executed at a predetermined time interval, when the luminance levels of the adjacent dots are different, such amounts of the charges charged in the parasitic capacitors C1 and C2 are not equal, so that the voltages are difficult to be returned to the intermediate voltage VM. Further, in the cases of JP-A-11-95729 and JP-A-2002-229525, since a circuit scale increases, there are problems to be solved such as increase in area of a chip and increase in costs.